(1) Field of the Invention
The present invention relates to semiconductor fabrication processes used to create hemispherical grain polysilicon.
(2) Description of Prior Art
The ability to fabricate polysilicon, exhibiting hemispherical grains, has found several applications in semiconductor chips. However the primary application for hemispherical grain, (HSG), polysilicon, has been its use in dynamic random access memory, (DRAM), devices. DRAM devices, using a stacked capacitor structure, (STC), is capacitance limited, by the dimensions of the capacitor. The STC structure, overlying a transfer gate transistor, is limited in area to the dimension of the underlying transistor structure. Therefore to obtain greater capacitance for DRAMs using the STC structure, the semiconductor industry has attempted to increase the surface area of the storage node, or lower electrode, of the STC structure, without increasing the area used by the STC structure. This has been accomplished via use of a lower electrode, comprised of a roughened silicon surface. The roughened silicon surface, supplies a greater surface area than counterparts with smooth surfaces.
One method for obtaining roughened silicon surfaces, has been the use of HSG polysilicon. HSG polysilicon surfaces are characterized by concave and convex features, thus resulting in an increase in surface area. However the magnitude of the surface area increase, and thus the increase in STC capacitance, is a function of the degree of roughness of the HSG polysilicon. Watanabe, et al, in an article, "Hemispherical Grain Silicon for High Density DRAMS, in SOLID STATE TECHNOLOGY, July 1992, pages 29-33, describe a method of directly depositing HSG polysilicon, without the use of a subsequent anneal step. However that process demands a narrow temperature range needed for attainment of HSG polysilicon. Liao, et al, in U.S. Pat. No. 5,583,070, describe a DRAM device, using an STC structure, in which an HSG polysilicon layer, again supplies the top surface for the lower electrode of the STC structure. In this invention an amorphous layer of polysilicon is first deposited, followed by an in situ anneal, resulting in the HSG polysilicon.
The present invention will describe a process for producing HSG polysilicon, using a specific, and unique set of deposition and anneal conditions, different than conditions described in the prior art. The use HSG polysilicon, used as part of the lower electrode of a STC structure, and obtained using the conditions described in this invention, increase the capacitance of of a plane plate test structure, by about 100%, when compared to counterparts fabricated without the use of the HSG polysilicon layer, described in this invention. This HSG polysilicon layer, when used for either 4 Mb, or 16 Mb, DRAM cells, result in capacitance increases of about 50%, when compared to counterpart DRAM devices, fabricated without HSG polysilicon.